###############################################################################
## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

set FPGA_ID 0x04b31093
set FW_ID 0x00000000
set FW_VER 0x00000100
set BOARD_ID 0x10ee9076
set BOARD_VER 0x01000000
set BUILD_DATE 0x17320231
set GIT_HASH 0x37f26075
set RELEASE_INFO 0x00000000
set IF_COUNT 1
set PORTS_PER_IF 1
set SCHED_PER_IF 1
set PORT_COUNT 1
set CLK_PERIOD_NS_NUM 4
set CLK_PERIOD_NS_DENOM 1
set PTP_CLK_PERIOD_NS_NUM 32
set PTP_CLK_PERIOD_NS_DENOM 5
set PTP_CLOCK_PIPELINE 0
set PTP_CLOCK_CDC_PIPELINE 0
set PTP_SEPARATE_TX_CLOCK 0
set PTP_SEPARATE_RX_CLOCK 0
set PTP_PORT_CDC_PIPELINE 0
set PTP_PEROUT_ENABLE 1
set PTP_PEROUT_COUNT 1
set EVENT_QUEUE_OP_TABLE_SIZE 32
set TX_QUEUE_OP_TABLE_SIZE 32
set RX_QUEUE_OP_TABLE_SIZE 32
set CQ_OP_TABLE_SIZE 32
set EQN_WIDTH 6
set TX_QUEUE_INDEX_WIDTH 13
set RX_QUEUE_INDEX_WIDTH 8
set CQN_WIDTH 14
set EQ_PIPELINE 3
set TX_QUEUE_PIPELINE 4
set RX_QUEUE_PIPELINE 3
set CQ_PIPELINE 5
set TX_DESC_TABLE_SIZE 32
set RX_DESC_TABLE_SIZE 32
set RX_INDIR_TBL_ADDR_WIDTH 8
set TX_SCHEDULER_OP_TABLE_SIZE 32
set TX_SCHEDULER_PIPELINE 4
set TDMA_INDEX_WIDTH 6
set PTP_TS_ENABLE 1
set PTP_TS_FMT_TOD 0
set PTP_TS_WIDTH 48
set TX_CPL_ENABLE 1
set TX_CPL_FIFO_DEPTH 32
set TX_TAG_WIDTH 16
set TX_CHECKSUM_ENABLE 1
set RX_HASH_ENABLE 1
set RX_CHECKSUM_ENABLE 1
set PFC_ENABLE 1
set LFC_ENABLE 1
set MAC_CTRL_ENABLE 0
set TX_FIFO_DEPTH 131072
set RX_FIFO_DEPTH 131072
set MAX_TX_SIZE 9214
set MAX_RX_SIZE 9214
set TX_RAM_SIZE 131072
set RX_RAM_SIZE 131072
set DDR_ENABLE 0
set DDR_CH 1
set DDR_GROUP_SIZE 1
set AXI_DDR_DATA_WIDTH 256
set AXI_DDR_ADDR_WIDTH 32
set AXI_DDR_STRB_WIDTH 32
set AXI_DDR_ID_WIDTH 8
set AXI_DDR_AWUSER_ENABLE 0
set AXI_DDR_WUSER_ENABLE 0
set AXI_DDR_BUSER_ENABLE 0
set AXI_DDR_ARUSER_ENABLE 0
set AXI_DDR_RUSER_ENABLE 0
set AXI_DDR_MAX_BURST_LEN 256
set AXI_DDR_NARROW_BURST 0
set AXI_DDR_FIXED_BURST 0
set AXI_DDR_WRAP_BURST 0
set HBM_ENABLE 0
set HBM_CH 1
set HBM_GROUP_SIZE 1
set AXI_HBM_DATA_WIDTH 256
set AXI_HBM_ADDR_WIDTH 32
set AXI_HBM_STRB_WIDTH 32
set AXI_HBM_ID_WIDTH 8
set AXI_HBM_AWUSER_ENABLE 0
set AXI_HBM_AWUSER_WIDTH 1
set AXI_HBM_WUSER_ENABLE 0
set AXI_HBM_WUSER_WIDTH 1
set AXI_HBM_BUSER_ENABLE 0
set AXI_HBM_BUSER_WIDTH 1
set AXI_HBM_ARUSER_ENABLE 0
set AXI_HBM_ARUSER_WIDTH 1
set AXI_HBM_RUSER_ENABLE 0
set AXI_HBM_RUSER_WIDTH 1
set AXI_HBM_MAX_BURST_LEN 256
set AXI_HBM_NARROW_BURST 0
set AXI_HBM_FIXED_BURST 0
set AXI_HBM_WRAP_BURST 0
set APP_ENABLE 1
set APP_ID 0x12340001
set APP_CTRL_ENABLE 1
set APP_DMA_ENABLE 1
set APP_AXIS_DIRECT_ENABLE 1
set APP_AXIS_SYNC_ENABLE 1
set APP_AXIS_IF_ENABLE 1
set APP_STAT_ENABLE 1
set APP_GPIO_IN_WIDTH 32
set APP_GPIO_OUT_WIDTH 32
set AXI_DATA_WIDTH 512
set AXI_ADDR_WIDTH 64
set AXI_STRB_WIDTH 64
set AXI_ID_WIDTH 8
set DMA_IMM_ENABLE 0
set DMA_IMM_WIDTH 32
set DMA_LEN_WIDTH 16
set DMA_TAG_WIDTH 16
set RAM_ADDR_WIDTH 17
set RAM_PIPELINE 2
set AXI_DMA_MAX_BURST_LEN 256
set AXI_DMA_READ_USE_ID 0
set AXI_DMA_WRITE_USE_ID 1
set AXI_DMA_READ_OP_TABLE_SIZE 256
set AXI_DMA_WRITE_OP_TABLE_SIZE 256
set IRQ_COUNT 8
set AXIL_CTRL_DATA_WIDTH 32
set AXIL_CTRL_ADDR_WIDTH 24
set AXIL_CTRL_STRB_WIDTH 4
set AXIL_IF_CTRL_ADDR_WIDTH 24
set AXIL_CSR_ADDR_WIDTH 19
set AXIL_CSR_PASSTHROUGH_ENABLE 0
set RB_NEXT_PTR 0x00001000
set AXIL_APP_CTRL_DATA_WIDTH 32
set AXIL_APP_CTRL_ADDR_WIDTH 24
set AXIL_APP_CTRL_STRB_WIDTH 4
set AXIS_DATA_WIDTH 512
set AXIS_KEEP_WIDTH 64
set AXIS_SYNC_DATA_WIDTH 512
set AXIS_IF_DATA_WIDTH 512
set AXIS_TX_USER_WIDTH 17
set AXIS_RX_USER_WIDTH 49
set AXIS_RX_USE_READY 0
set AXIS_TX_PIPELINE 4
set AXIS_TX_FIFO_PIPELINE 4
set AXIS_TX_TS_PIPELINE 4
set AXIS_RX_PIPELINE 4
set AXIS_RX_FIFO_PIPELINE 4
set STAT_ENABLE 1
set STAT_DMA_ENABLE 1
set STAT_AXI_ENABLE 1
set STAT_INC_WIDTH 24
set STAT_ID_WIDTH 12
set DMA_ADDR_WIDTH_APP 64
set RAM_SEL_WIDTH_APP 3
set RAM_SEG_COUNT_APP 2
set RAM_SEG_DATA_WIDTH_APP 512
set RAM_SEG_BE_WIDTH_APP 64
set RAM_SEG_ADDR_WIDTH_APP 10
set AXIS_SYNC_KEEP_WIDTH_APP 64
set AXIS_SYNC_TX_USER_WIDTH_APP 17
set AXIS_SYNC_RX_USER_WIDTH_APP 49
set AXIS_IF_KEEP_WIDTH_APP 64
set AXIS_IF_TX_ID_WIDTH_APP 13
set AXIS_IF_RX_ID_WIDTH_APP 1
set AXIS_IF_TX_DEST_WIDTH_APP 4
set AXIS_IF_RX_DEST_WIDTH_APP 9
set AXIS_IF_TX_USER_WIDTH_APP 17
set AXIS_IF_RX_USER_WIDTH_APP 49
set TDMA_BER_ENABLE 0
set QSFP_CNT 1
set PORT_MASK 0
set ETH_RX_CLK_FROM_TX 0
set ETH_RS_FEC_ENABLE 1
set DMA_ADDR_WIDTH 64
set RAM_SEL_WIDTH 3
set RAM_SEG_COUNT 2
set RAM_SEG_DATA_WIDTH 512
set RAM_SEG_BE_WIDTH 64
set RAM_SEG_ADDR_WIDTH 10
set AXIS_SYNC_KEEP_WIDTH 64
set AXIS_SYNC_TX_USER_WIDTH 17
set AXIS_SYNC_RX_USER_WIDTH 49
set AXIS_IF_KEEP_WIDTH 64
set AXIS_IF_TX_ID_WIDTH 13
set AXIS_IF_RX_ID_WIDTH 1
set AXIS_IF_TX_DEST_WIDTH 4
set AXIS_IF_RX_DEST_WIDTH 9
set AXIS_IF_TX_USER_WIDTH 17
set AXIS_IF_RX_USER_WIDTH 49
